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Get A Designer s Guide to Built-in Self-Test PDF

By Charles E. Stroud

ISBN-10: 1402070500

ISBN-13: 9781402070501

A up to date technological increase is the paintings of designing circuits to check themselves, known as a integrated Self-Test (BIST). This inspiration used to be first proposed round 1980 and has grown to develop into one of many most crucial checking out ideas on the present time, in addition to for the long run. This publication is written from a designer's point of view and describes the main BIST ways which were proposed and carried out considering the fact that 1980, besides their merits and barriers. The BIST ways contain the integrated common sense Block Observer, pseudo-exhaustive BIST recommendations, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection options for online checking out. specific consciousness is paid to system-level use of BIST so that it will maximize some great benefits of BIST via lowered trying out time and value in addition to excessive diagnostic solution. the writer spent 15 years as a clothier at Bell Labs the place he designed over 20 construction VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied forms for normal constructions and common sequential common sense, together with the first BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal platforms at Bell Labs. He has spent the earlier 10 years in academia the place his learn and improvement maintains to target BIST, together with the first BIST for FPGAs and CPLDs besides persevered paintings within the sector of BIST for normal sequential good judgment and mixed-signal structures. He holds 10 US patents (with five extra pending) for numerous varieties of BIST methods. for that reason, the writer brings a different mix of information and event to this sensible advisor for designers, try out engineers, product engineers, procedure diagnosticians, and executives.

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Additional resources for A Designer s Guide to Built-in Self-Test

Example text

The faulty behavior illustrated assumes that only one fault is present in the gate. The output responses that differ from those of the fault-free gate are highlighted in gray. For the transistor stuck-on faults, some input patterns will produce a conducting path from to through the output node during steady-state due to the fault condition. As a result, the voltage at the output node will not be equal to either or but will instead be a function of the voltage divider formed by the channel resistance of the conducting transistors.

These faults are common defects that result from over-etching or under-etching during the VLSI or PCB fabrication process. Since an open in a wire prevents the propagation of a signal past the open, inputs to gates and transistors on the other side of the open will remain constant, creating behavior equivalent to the gate-level and transistor-level fault models. As a result, opens can be detected by test vectors for either gate-level or transistor-level fault models. Therefore, only shorts between wires are of interest and they are more commonly referred to as bridging faults.

Fault simulation also provides valuable information on portions of the design that need further design verification (as we shall discuss shortly). The design verification vectors are often used as functional vectors during manufacturing testing. The test machine, also referred to as the automatic test equipment (ATE), applies the test vectors to the fabricated circuit and compares the output responses to the expected responses obtained from the design verification simulation environment for the fault-free (and hopefully, design error-free) circuit.

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A Designer s Guide to Built-in Self-Test by Charles E. Stroud


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